CW5521

The newest and highest performance generation of the CWvX DSP architecture is now available in the CW5xxx series of processors.  The first member of this family is the CW5521, a combination of RISC processing and sixteen parallel vector processing units supplemented by more embedded memory and a more diverse instruction set than any other ChipWrights DSP.  Capable of more MMACS per mW than any other DSP, the CW5521 brings the flexibility of programmable processing to markets traditionally restricted to fixed function ASICs.

MMACS	19,200 (maximum)
Maximum DSP Clock Frequency	300MHz
Primary Memory	256KB
Instruction Cache	16KB
External Memory Interface	32-bit DDR SDRAM
Parallel Input Interface	8-bit, 16-bit, 32-bit
Parallel Output Interface	8-bit or 16-bit, 3x 10-bit DAC
Timer Modules	4 Programmable, 1 Watchdog
Host/Slave Support	8-bit or 16-bit asynchronous, 8 chip selects
DMA Channels	8
Removable Storage	CompactFlash, SecureDigital
USB	2.0 HS (480 Mbps)
Core Voltage	1.0-1.2V
IO Voltage	3.3V (2.5V DDR SDRAM)
Package	496-pin BGA (0.65 mm ball pitch)

Advanced CWv16 Single Instruction Multiple Datapath (SIMD) DSP Engine

·           16 parallel vector processing units

·           Serial RISC control processor

·           Up to 19,200 Million Multiply Accumulates per Second (MMACS)

·           Very Dense Instruction Word™ (VDIW) Technology

►          Provides the benefits of VLIW™ in a 32-bit instruction

·           Sub-word parallelism allows multiple operands in packed data formats

·           Each vector processor can access its own memory area simultaneously

·           Thirty-one 32-bit registers per vector processor

·           One 96-bit accumulator per vector processor

New instructions for enhanced multimedia processing capability

·           Parallel memory access for packed data types

·           Logical serial shift operations

·           Inverted parallel branching

·           Post-iteration incrementing for serial loops

·           4-bit multiplication improvements

·           Enhanced debugging capability

Special instructions to accelerate image processing

·           Operate on packed byte and word data types

·           Strided and table memory access

·           Sum of absolute differences for motion estimation calculations

·           Dot product for color space conversion

·           Saturate operators for clamping

256 KB embedded data memory

Extensive instruction cache

·           16 KB direct mapped cache holds 4,096 32-bit instructions

·           64-byte block size with lock capability

External memory interface

·           16-bit or 32-bit DDR SDRAM interface

·           512 MB (maximum)

·           Write FIFO to increase system bus performance

·           Speculative pre-fetch buffers to reduce average read latency

8 independent DMA channels

·           Embedded to external memory

·           External to embedded memory

·           Video input to memory

·           Memory to video output

·           USB to memory/memory to USB

·           SD to memory/memory to SD

·           JPEG Encoder to memory

·           Memory to JPEG encoder

Dual 32-bit internal AHB system bus

Dedicated hardware JPEG encoder with associated direct memory access

Parallel/Video input port

·           8-bit or 16-bit configurable input

·           Sync pulse generation for CCD/CMOS image sensor interface

Parallel/Video output port

·           8-bit or 16-bit configurable output

·           Sync pulse generation for driving digital display

·           Three 10-bit DACs for driving analog displays

·           Support for CVBS, RGB555, RGB565, and RGB545

Host/Peripheral interface

·           Connects to off-chip peripherals, such as boot ROM, when acting as system host processor

·           Connects to host processor when acting as a co-processor

·           CompactFlash and ATA/ATAPI device support

Audio CODEC interface

·           Interface to I2S audio devices

USB 2.0HS support

·           Up to 480 Mbps

Dual Synchronous serial interface

·           Supports SPI and Microwire™ protocols

16550 compatible UART port

147 general purpose input/output pins (48 dedicated, 99 multiplexed)

4 programmable 32-bit timer/counters

One Watchdog timer

Pulse Width Modulator interface for stepper motor control

IEEE-1149.1 compatible JTAG interface

·           Supports boundary SCAN

·           Allows real-time debugging with ChipWrights development environment

496-pin ball grid array (BGA) package

·           0.65 mm ball pitch

0.13 um technology

Variable core voltage (1.0V-1.2V)

·           Determines the best performance and power settings for the application

3.3V IO voltage

2.5V DDR SDRAM voltage

Less than 1 W typical power consumption at 1.2V