CW4512 System on Chip Specification Table

CW4512 System-on-Chip Specification Table

System-on-Chip Components

CWv8 SIMD DSP Engine	8 parallel vector processing units Serial RISC control processor 6,400 MMACs (maximum) Very Dense Instruction Word (VDIW) technology - Provides benefit of VLIW in a 32-bit instruction Sub-word parallelism allows multiple operands in packed data formats Vector processor units can access their processor units simultaneously Thirty-one 32-bit registers per vector processor One 96-bit accumulator per vector processor
Special instructions to accelerate image processing	Operate on packed byte and word data types Strided and table memory access Sum of absolute differences for motion estimation calculations Dot product for color space conversion Saturate operators for clamping
Embedded data memory	128 KB
Extensive instruction cache	8 KB direct mapped cache holds 2,048 thirty-two bit instructions 32-byte block size with lock capability
External memory interface	16- or 32-bit SDRAM interface 256MB (maximum)
Independent DMA channels (6)	Embedded to external memory External to embedded memory Video input to memory Memory to video output USB to memory/memory to USB SD to memory/memory to SD
Video Interface	16-bit Digital Video Input/Output; ITU-R BT.601, ITU-R BT.656 16-bit Digital Video Output; High-Definition Multimedia Interface (HDMI) Compatible NTSC/PAL TV Encoder Quad 10-bit Video DAC Hardware OSD Assist Programmable Video Input/Output Timing Generators Programmable data formatting logic; adjust data width, order, polarity, and padding Programmable control logic; interface to wide variety of data sources and destinations
32-bit internal high speed AHB system bus
Parallel/Video input port	8- or 16-bit configurable input Sync pulse generation for CCD/CMOS image sensor interface
Parallel/Video output port	8-bit or 16-bit configurable output Sync pulse generation for driving digital display Three 10-bit DACs for driving analog displays Support for CVBS, RGB555, RGB565, and RGB545
Host/Peripheral interface	Interfaces to I2S audio devices
Audio CODEC interface	96 GPIO; 24 dedicated, 72 shared 3 Pulse Width Modulator (PWM); 2 wires each for motor control
USB support	1.1
SSI	Supports SPI and Microwire™ protocols
16550 compatible UART port
56 GPIO pins	32 dedicated 24 multiplexed
Timers	4 programmable 32-bit timers/counters 1 watchdog timer
PWM interface	3 Stepper motor controls
IEEE-1149.1 compatible JTAG interface	Supports boundary SCAN Allows real time debugging within ChipWrights development environment
Ball grid array	256-pin package 1.0 mm ball pitch
0.18 um technology
Voltage	1.6V core 3.3V IO
Power consumption	750 mW typical at 1.6V
System-on-Chip Performance
MMACS	6,720 (maximum)
Maximum DSP Clock Frequency	210MHz
Primary Memory	128KB
External Memory	32-bit SDRAM
Instruction Cache	8KB
Parallel Input Interface	8 or 16-bit digital
Parallel Output Interface	Parallel Output Interface 8 or 16-bit digital, 3x10-bit DAC
Timer Modules	4 programmable, 1 watchdog
Host/Slave Support	8 or 16-bit asynchronous
DMA Channels	6
Removable Storage	CompactFlash®, SecureDigital
USB	1.1
Core Voltage	1.6V
IO Voltage	3.3V
Package	256-pin BGA (1.0mm ball pitch)